Areas of Interest

  Classes

Fall 2008

• CS 414: Operating Systems (undergraduate)

Prior courses taught - undergraduate:

• CS 433: Advanced Computer Architecture, spring 2007
• CS 414:  Operating Systems, spring 2002, 2004, 2005, 2006
• CS 451: Advanced Processor Architecture, fall 2005
• CS 493/693: Independent study - Architecture Simulation Methodology, spring 2006
• CS 390: Senior Seminar I, spring 2000

Prior courses taught - graduate:

• CS 754: Advanced Computer Architecture, fall 2006
• CS 793: Independent Study - Parallel and Multicore Architectures, spring 2007
• ECE 687: Physically-Aware Design (seminar, co-taught with John Lach and Mircea Stan), spring 2006
• CS 654: Computer Architecture, fall 2000, 2001, 2002, 2003, 2004
• CS 851: Advanced Topics: High Performance Micro-Architectures for Computer Graphics, fall 2004 (co-taught with David Luebke)
• CS 851:  Special Topics in Computer Architecture: Keeping Chips Cool, spring 2002 (co-taught with Mircea Stan)
• CS 854/551: Advanced Computer Architecture: A Microprocessor Survey, spring 2001
• CS 851: Aggressive Speculative Microarchitectures, spring 2000
• CS 551/851: A Microprocessor Survey, fall 1999

 Biographical Sketch

Skadron is a member of Eta Kappa Nu, Omicron Delta Epsilon, and a senior member of the IEEE and ACM. For the year 2003-04, he was named a University of Virginia Teaching Fellow.  Among other professional activities, he is founding associate editor-in-chief of  IEEE Computer Architecture Letters, serves on the editorial board of IEEE Micro, and on the technical advisory board of Gradient-DA.  He is secretary-treasurer of ACM's SIGARCH and has also served as guest co-editor of a special issue in IEEE Computer on Power-Aware and Temperature-Aware Computing, technical program co-chair of PACT 2006, general co-chair for PACT 2002 and MICRO-37,  and co-organizer of the Workshop on Temperature Aware Computer Systems.

Note to graduate student and summer-intern applicants

Inquiries from prospective graduate students: Due to the large number of these inquiries, please understand that I am not able to respond to form letters.  Of course I am always happy to discuss mutual research interests.

  Research

In recent years power dissipation has become an area of intense concern to the designers of microprocessors for a variety of reasons. In sub-45nm and subvolt technologies, transistor size decreases much more rapidly than power per device, leading to increasing power densities.  This in turn requires sophisticated and expensive thermal packages to control heat dissipation, but we are approaching the limits of air cooling.  Battery life and energy consumption are also perennial concerns.  Reducing power dissipation helps mitigate all these problems, although controlling temperature requires different low-power strategies than for energy efficiency.  While circuit-level techniques have been a mainstay for years for managing power dissipation, architecture-level techniques offer the promise of additional and synergistic techniques for managing power because they can take advantage of additional knowledge about the runtime behavior of the current workload.  Unfortunately, most architecture-level power- and thermal-management techniques impede processing speed, because they operate by turning off or slowing down part or all of the processor.  The challenge therefore lies in finding power- and thermal-management techniques that minimize the consequent loss in performance.  A complicating factor is that process variations, which affect both circuit speed and power (especially leakage), will increasingly complicate power and thermal management as well as reliability. 

A further challenge is the advent of multiple cores on a chip.  Power constraints limit the exponential growth in clock speeds that we have become accustomed to, and instead Moore's Law will increasingly be realized by growth in the number of cores or processing elements on a single chip.  This raises a host of new questions, such as number of cores, type of cores, etc.--all of which must be selected to optimize energy and thermal efficiency.  A complicating factor is that power, thermal, and performance design variables are inter-related: optimizing the architecture of a single core and then replicating that, or optimizing the multicore architecture without simultaneously considering the impact of thermal limits, will produce a radically suboptimal design, with no obvious way to scale that design to approximate optimality.  Parameter variations complicate this even further.  For example, we show that process variations make it difficult to achieve symmetric performance among cores on a multicore chip without investing in a more expensive cooling solution. 

The most likely response to these trends is toward organizations that emphasize thread or data parallelism over single-thread performance and ILP and use specialized hardware (in the form of coprocessors or special functional units) when possible.  Both approaches reduce energy per operation.  In order to investigate these issues, we have been using NVIDIA's CUDA general-purpose programming language.  CUDA presents a few, easy-to-learn abstractions for parallel programming, and GPUs provide parallelism at scales that expose interesting programming and architectural issues--a fully occupied Tesla-architecture GPU multiplexes 12k simultaneously-resident threads onto 128 processing elements.  We are interested in how to draw the boundaries between CPU and GPU resources, cache and interconnect architecture,  synchronization mechanisms, and programming models.  We are especially interested in how to design manycore architectures that support convenient programming models while preserving the ability to "drill down" when necessary.  To support this work, we are developing a suite of benchmark applications which we will release shortly.

In prior work, my group has:

• Described new mechanisms for lightweight out-of-order execution and how to use this to federate small, in-order, throughput oriented cores into an OO core on demand--this fusion provides as many OO cores as necessary and avoids wasting chip area on dedicated OO cores.
• Described a new form of neural branch predictor
• Described power-management techniques for branch prediction that do not impede prediction accuracy or performance
• Evaluated the optimal energy-efficient scaling of microarchitectural structure sizes for simultaneous multithreading (SMT)
• Evaluated whether trace caches are energy efficient
• Described how to optimize power subject to real-time constraints in multi-tier servers, including the case of multiple priority classes.  We plan to explore how to extend this work to other forms of task pipelines.
• Proposed feedback-control for DVS with multimedia workloads
• Explored the interaction between thermal management and reliability
• Explored how current power and thermal management features may expose security vulnerabilities
• Shown the value of control theory in managing adaptive hardware structures, including controlling the DVS setting for a multimedia workload; setting the decay interval for leakage-power management using cache decay; and thermal regulation

Of course, to support this research, application characterization and new simulation techniques are always of interest.  To this end we have developed the HotLeakage and HotSpot  leakage/temperature models, and we are continuing our modeling efforts in these areas.  We have also developed the MRRL technique for fast and provably accurate warm-up when moving between many smaller samples.  In the area of graphics architecture, we developed the Qsilver simulation framework.

These research projects have stimulated several innovations in our computer architecture courses, including the development of a Microprocessor Survey Course (also described in a paper at SIGCSE) and the use of CUDA to teach both concurrency and parallel architecture.

This work is currently supported by the National Science Foundation under grant nos. CNS-0509245, CNS-0551630 (CRI), IIS-0612049, and CNS-0615277; research grants from Intel MTL , the Semiconductor Research Corporation under grant no. 1607; and a research grant and equipment donations from NVIDIA.  Prior support has come from the National Science Foundation under grant nos. ITR-0082671, CCR-0133634 (CAREER), CCR-0105626, EIA-0224434, DOS-0306404, and CCF-0429765; the Army Research Office under grant no. W911NF-04-1-0288;  IBM Research;  and an Excellence Award from the University of Virginia Fund for Excellence in Science and Technology.  Additional support has been provided by William A. Ballard Fellowships for John W. Haskins and David Tarjan, a University of Virginia Award for Excellence in Scholarship in the Sciences & Engineering for David Tarjan, and an ATI graduate fellowship for Jeremy Sheaffer.  Please note that any opinions, findings, and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the funding agencies.

Graduate Students:

• Marco Barcella (MSEE, 2002), U.Va. ECE (advisor: Mircea Stan) - now with Appian Corp.
• Michael Boyer
• Shuai Che
• Michele Co (Ph.D., 2006) - now a Research Associate, U.Va. CS
• John Haskins (Ph.D., 2003) - now with NVIDIA
• Kevin Hirst (MCS, 2002) - now with Inova.
• Tibor Horvath
• Wei Huang (Ph.D., 2006), U.Va. ECE (advisor: Mircea Stan)  - now a Research Associate, U.Va. CS
• Eric Humenay (ME, 2007) -  now with RLW, Inc.
• Yingmin Li (Ph.D., Aug. 2006) - now with NVIDIA
• Zhijian Lu (Ph.D., Jan. 2007), U.Va. ECE (advisor: John Lach) - now with Marvell Technology
• Jiayuan Meng
• Dharmesh Parikh (MCS, 2003) - now with AMD
• Karthik Sankaranarayanan
• Jeremy Sheaffer (Ph.D., 2007) Now seeking academic and research positions
• Lukasz Szafaryn
• David Tarjan
• Sivakumar Velusamy (MCS, 2005) - now with Xilinx
• Dee A.B. Weikle (Ph.D., 2001) - now a Research Scientist, U.Va. CS
• Chris White (MCS, 2007) - now with Electronic Arts

Undergraduate Researchers:

• Henry "Drew" Abbot '07
• Sean Arietta '08
• Adam Banda '07
• Clay Carter '07
• David C. Chu '04, now a Ph.D. student at UC-Berkeley
• Henry Cook '07, now a Ph.D. student at UC-Berkeley
• Steve Cook '07
• Puyan Dadvar '05
• David Faulkner '06
• Jesse Foster '05
• Shougata Ghosh '05, now a Ph.D. student at Princeton
• Philo Juang '00, Ph.D. '05 Princeton EE, now with Google
• Michael King '02
• Adrian Lanning '00
• Kyeong-Jae Lee '05, now a Ph.D. student at MIT
• Drew Maier '07
• Daniel Marcus '07
• David McWhorter '05
• Anindo Mukherjee '06
• Eugene Otto '06
• Chris Palmer '07
• Pitchaya Sitthi-Amorn '07
• Kevin Stammetti '07
• Tiffany Tsai '07
• Robert Zhu '05

• More about Skadron's research in the LAVA Lab
• Tutorial on NVIDIA GPU programming (CUDA), with David Luebke (NVIDIA Research), Michael Garland (NVIDIA Research), and John Owens (UC Davis), at ASPLOS-XIII, Seattle, WA, Mar. 2008.
• Tutorial on Thermal Issues for Temperature-Aware Computer Systems, with David Brooks (Harvard), Antonio Gonzalez (UPC Barcelona and Intel Barcelona), Lev Finkelstein (Intel Haifa), and Mircea R. Stan (Univ. of Virginia), at ISCA-31, Munich Germany, June 2004.
• Tutorial on Power-Aware Design for High-Performance Processors, with José González (Intel Barcelona), at HPCA-10, Madrid Spain, Feb. 2004.
• HotSpot software
• HotLeakage software release
• Qsilver graphics architecture simulation framework
• MRRL (Memory Reference Reuse Latency) home page
• HydraScalar home page
• Notes for how to be a successful conference publications chair; also a template (courtesy of Martin Schulz) for a receipt to send for extra-page charges
• Good advice on how to succeed as a graduate student (from Christos Kozyrakis's website)
• Position papers & final report, 2001 NSF Workshop on Computer Performance Evaluation, co-organized with Margaret Martonosi.  The panel's recommendations also appear in an article in the Aug. 2003 issue of IEEE Computer.

  Selected Publications

Recent Highlights

• (thermal) W. Huang, K. Sankaranarayanan, K. Skadron, R. J. Ribando, and M. R. Stan.  "Accurate, Pre-RTL Temperature-Aware Processor Design Using a Parameterized, Geometric Thermal Model."  IEEE Transactions on Computers, to appear. (preprint pdf)

• (manycore, thermal) W. Huang, M. R. Stan, K. Sankaranarayanan, Robert J. Ribando, and K. Skadron. “Many-Core Design from a Thermal Perspective.”  In Proceedings of the 45th ACM/IEEE Conference on Design Automation (DAC), June 2008, to appear.  (pdf)

• (manycore) D. Tarjan, M. Boyer, and K. Skadron. “Federation: Repurposing Scalar Cores for Out-of-Order Instruction Issue.” In Proceedings of the 45th ACM/IEEE Conference on Design Automation (DAC), June 2008, to appear. (pdf)

• (simulation methodology) H. Cook and K. Skadron. “Predictive Design Space Exploration Using Genetically Programmed Response Surfaces.” In Proceedings of the 45th ACM/IEEE Conference on Design Automation (DAC), June 2008, to appear. (pdf)

• (gpgpu) J. Nickolls, I. Buck, M. Garland, K. Skadron.  “Scalable Parallel Programming with CUDA.”  ACM Queue, 6(2):40-53, Mar.-Apr. 2008.  DOI 10.1145/1365490.1365500 (pdf)

• (gpgpu, program analysis) M. Boyer, K. Skadron, and W. Weimer. “Automated Dynamic Analysis of CUDA Programs.” In Proceedings of the Third Workshop on Software Tools for MultiCore Systems (STMCS), in conjunction with the IEEE/ACM International Symposium on Code Generation and Optimization (CGO), Apr. 2008. (pdf)

• (manycore) D. Tarjan and K. Skadron.  “Multithreading vs. Streaming”  Position paper in Proceedings of the SIGPLAN Workshop on Memory Systems Performance and Correctness, Mar. 2008. (pdf)

• (power, branch prediction) S. W. Chung and K. Skadron.  “On-Demand Solution to Minimize I-Cache Leakage Energy with Maintaining Performance.”  IEEE Transactions on Computers, 57(1):7-24, Jan. 2008, DOI 10.1109/TC.2007.70770. (pdf)

• (power, thermal) K. Skadron, P. Bose, K. Ghose, R. Sendag, J. J. Yi, and D. Chiou. "Low-Power Design and Temperature Management." IEEE Micro, 27(6):46-57, Nov.-Dec. 2007. DOI 10.1109/MM.2007.104.  (pdf)

• (gpgpu) S. Che, J. Meng, J. W. Sheaffer, and K. Skadron.  “A Performance Study of General Purpose Applications on Graphics Processors.”  First Workshop on General Purpose Processing on Graphics Processing Units, Northeastern University, Oct. 2007.  (pdf)

• (graphics architecture, reliability) J. Sheaffer, D. Luebke, and K. Skadron. “A Hardware Redundancy and Recovery Mechanism for Reliable Scientific Computation on Graphics Processors.” In Proceedings of Eurographics/ACM Graphics Hardware 2007 (GH), pp. 55-64, Aug. 2007. (pdf)

• (parameter variations, multicore, thermal, power, leakage) E. Humenay, D. Tarjan, and K. Skadron.  "Impact of Process Variations on Multicore Performance Symmetry."  In Proceedings of the 2007 Conference on Design, Automation and Test in Europe (DATE), pp. 1653-58, Apr. 2007.  (pdf)

• (power, real-time) T. Horvath, T. Abdelzaher, and K. Skadron. “Dynamic Voltage Scaling in Multi-tier Web Servers with End-to-end Delay Control.” IEEE Transactions on Computers, 56(4):444-58, Apr. 2007.  (pdf)

Highlights from Prior Work

• (reliability, thermal) Z. Lu, W. Huang, M. Stan, K. Skadron, and J. Lach.  “Interconnect Lifetime Prediction for Reliability-Aware Systems.”  IEEE Transactions on VLSI Systems, 15(2):159-72, Feb. 2007.  (pdf)

• (branch prediction, trace cache, power) M. Co, D. A.B. Weikle, and K. Skadron. "Evaluating Trace Cache Energy Efficiency." ACM Transactions on Architecture and Code Optimization (TACO), 3(4):450-76, Dec. 2006. (Abstract | pdf)

• (power, multimedia, real-time) Z. Lu, J. Lach, K. Skadron, and M. R. Stan. “Design and Implementation of an Energy Efficient Multimedia Playback System.” In Proceedings of the 40th Asilomar Conference on Signals, Systems and Computers, Oct. 2006. (pdf)

• (graphics architecture, reliability) J. W. Sheaffer, D. P. Luebke, and K. Skadron. “The Visual Vulnerability Spectrum: Characterizing Architectural Vulnerability for Graphics Hardware.” In Proceedings of Eurographics/ACM Graphics Hardware 2006 (GH), pp. 9-16, Sept. 2006. (pdf)

• (thermal) S. W. Chung and K. Skadron. “Using on-Chip Event Counters for High-Resolution, Real-Time Temperature Measurements.” In Proceedings of the IEEE/ASME Tenth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITHERM), June 2006. (pdf)

• (power) Z. Lu, Y. Zhang, M. R. Stan, J. Lach, and K. Skadron.  “Procrastinating Voltage Scheduling with Discrete Frequency Sets.”   In Proceedings of the 2004 Design, Automation and Test in Europe Conference (DATE), pp. 456-61, Mar. 2006.  (pdf)

• (multi-core architecture, power, thermal) Y. Li, B. C. Lee, D. Brooks, Z. Hu, and K. Skadron.  "CMP Design Space Exploration Subject to Physical Constraints."  In Proceedings of the Twelfth IEEE International Symposium on High Performance Computer Architecture (HPCA), pp. 15-26, Feb. 2006. (pdf)

• (power) V. Narayanan and K. Skadron.  "Architectural/System Design and Optimization," in "CAD Algorithms, Methods and Tools For Low-Power Circuits and Systems," E. Macii ed. IEEE Council on Electronic Design Automation (C-EDA) Technology Survey, Jan. 2006.  (IEEE Xplore link)

• (thermal) K. Sankaranarayanan, S. Velusamy, M.R. Stan, and K. Skadron.  "A Case for Thermal-Aware Floorplanning at the Microarchitectural Level."  The Journal of Instruction-Level Parallelism, vol. 7, Oct. 2005, http://www.jilp.org/vol7/. (pdf)

• (branch prediction) D. Tarjan and K. Skadron. “Merging Path and Gshare Indexing in Perceptron Branch Prediction.” ACM Transactions on Architecture and Code Optimization, Sept. 2005, 2(3):280-300. (pdf)

• (power, thermal) Y. Li, M. Hempstead, P. Mauro, D. Brooks, Z. Hu, and K. Skadron. “Power and Thermal Effects of SRAM vs. Latch­Mux Design.” In Proceedings of the ACM/IEEE 2005 International Symposium on Low-Power Electronics Design (ISLPED), pp. 173-178, Aug. 2005.  (pdf)

• (thermal, security) P. Dadvar and K. Skadron.  “Potential Thermal Security Risks.”  In Proceedings of the IEEE Semiconductor Thermal Measurement, Modeling, and Management Symposium (Semi-Therm 21), pp. 229-34, Mar. 2005.  (pdf)

• (thermal, graphics architecture) J. W. Sheaffer, K. Skadron, and D. P. Luebke.  “Studying Thermal Management for Graphics-Processor Architectures.”  In Proceedings of the 2005 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), Mar. 2005.  (pdf | Qsilver software home page)

• (thermal) K. Skadron, K. Sankaranarayanan, S. Velusamy, D. Tarjan, M.R. Stan, and W. Huang.  “Temperature-Aware Microarchitecture: Modeling and Implementation.”  ACM Transactions on Architecture and Code Optimization, 1(1):94-125, Mar. 2004.  (pdf)

• (leakage power) Y. Li, D. Parikh, Y. Zhang, K. Sankaranarayanan, M. R. Stan, and K. Skadron.  “State-Preserving vs. Non-State-Preserving Leakage Control in Caches.”  In Proceedings of the 2004 Design, Automation and Test in Europe (DATE) Conference, pp. 22-27, Feb. 2004.  (pdf) [HotLeakage software home page]

• (power, real-time) V. Sharma, A. Thomas, T. Abdelzaher, Z. Lu, and K. Skadron.  “Power-Aware QoS Management on Web Servers.”  In Proceedings of the 24th International Real-Time Systems Symposium, pp. 63-72, Dec. 2003. (pdf) (Best student paper!)

• (branch prediction) Z. Lu, J. Lach, M. Stan, and K. Skadron.  “Alloyed Branch History: Combining Global and Local Branch History for Robust Performance,” International Journal of Parallel Programming, Kluwer, 31(2):137-77, Apr. 2003.  (pdf | Abstract)

• (write buffers) K. Skadron and D.W. Clark. "Design Issues and Tradeoffs for Write Buffers." In Proceedings of the Third International Symposium on High-Performance Computer Architecture, pp. 144-55, February 1997. (postscript | pdf | abstract)

  Software Releases

• HotSpot (includes HotFloorplan)
• HotLeakage
• Qsilver
• AmberBBV, for generating basic block vectors (e.g. for use with SimPoint) from Amber traces (part of the CHUD tools).
• MRRL tools
• HydraScalar

  The Next Generation