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Announcing version 5.0! New!

Version 5.0 introduces several new features that can be useful to special thermal modeling needs: 1) a parameterized heatsink and fan model; 2) secondary heat transfer path from silicon to C4 pads to packaging substrate to solder ball and printed-circuit board; 3) a simple leakage-temperature loop and interface for users to incorporate their own leakage power model. You can download version 5.0 here.

What is HotSpot?

HotSpot is an accurate and fast thermal model suitable for use in architectural studies. It is based on an equivalent circuit of thermal resistances and capacitances that correspond to microarchitecture blocks and essential aspects of the thermal package. The model has been validated using finite element simulation. HotSpot has a simple set of interfaces and hence can be integrated with most power-performance simulators like Wattch. The chief advantage of HotSpot is that it is compatible with the kinds of power/performance models used in the computer-architecture community, requiring no detailed design or synthesis description. HotSpot makes it possible to study thermal evolution over long periods of real, full-length applications.

Why thermal modeling?

With power density and hence cooling costs rising exponentially, temperature-aware design has become a necessity. Processor packaging is becoming a major expense, and for many chips can no longer be designed for the worst case. Furthermore, simple estimates of power dissipation are not a good proxy for direct measurement or simulation of temperature. There is an urgent need for design techniques to help control or reduce heat dissipation, especially runtime techniques that can regulate operating temperature when the package's capacity is exceeded. Runtime response provides safe cooling and prevents thermal emergencies by changing the processor's behavior rather than relying on costly thermal packaging. Evaluating such techniques, however, requires a thermal model that is practical for architectural studies, especially research or design-space investigations for which no detailed designs are yet available.

This material is based upon work supported by the National Science Foundation under grant nos. CCR-0133634, CCR-0105626, EIA-0224434, CCF-0429765, CNS-0509245, and CNS-0551630, the Army Research Office under grant no. W911NF-04-1-0288, and grants from IBM, Intel, and the Univ. of Virginia Fund for Excellence in Science and Engineering. Any opinions, findings, conclusions, or recommendations expressed in this material are those of the authors and do not necessarily reflect the views of the sponsoring agencies.

Last updated: June 11, 2014

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