Version History

• CHANGES IN VERSION 4.1
  1. The steady-state solver of the grid model has been upgraded from a Gauss-Seidel solver to a multigrid solver. This results in typical steady-state computation speedups > 20x. In order to facilitate the multigrid implementation, now the grid dimensions are required to be a power of two. Hence, the default grid size has been modified from 50x50 to 64x64.
  2. The simulator template (sim-template.c) that illustrates the use of HotSpot in a typical cycle-accurate simulator has been upgraded to include grid model usage. Earlier it only demonstrated the use of the block model (sim-template_block.c)
  3. The 'Makefile' has been upgraded to wrap HotSpot into a library (libhotspot.a) for easier integration with existing simulators.
  4. Bugfixes etc.:
     • A bug in 'hotspot.c' lead to erroneous power averaging in modeling 3-D chips while using the grid model. This has been fixed in this release.
     • A bug in the floorplan plotting script 'tofig.pl' caused temporary files not to be deleted. It has been fixed now.
     • Other minor changes like fixing typos etc.
  
  
• CHANGES IN VERSION 4.0
  1. Accuracy Enhancements:
     • Enhanced package modeling: removal of the forced isotherm
     • Modeling of lateral heat flow in the TIM layer
     • Block model: a wrapper script to sub-divide floorplan blocks with high aspect ratio to improve accuracy
     • Grid model: upgradation of the first order transient sover to a fourth order adaptive step-size Runge-Kutta solver
     • Grid model: an option to maintain grid thermal state across calls to the transient solver
  2. Updated defaults:
     The default package parameters have been updated to reflect contemporary packages. The most significant of the changes are:
     • Die thickness has been updated to 0.15 mm down from 0.5 mm. (See: B. Majeed, I. Paul, K. M. Razeeb, J. Barton and S. C. O'Mathuna. "Microstructural, Mechanical, Fractural and Electrical Characterization of Thinned and Singulated Silicon Test Die". Journal of Micromechanics and Microengineering, 16:1519-1529, Aug. 2006.)
     • Tim thickness and resistivity have been updated respectively to 20u down from 75u and 0.25 mK/W down from 0.75 mK/W. (See: E.C. Samson, S.V. Machiroutu, J.-Y. Chang, I. Santos, J. Hermerding, A. Dani, R. Prasher, and D.W.Song. "Interface Material Selection and a Thermal Management Technique in Second-Generation Platforms Built on Intel Centrino Mobile Technology." Intel Technology Journal, 9(1), Feb. 2005.)
  3. Others:
     • Complete re-write of the grid model for easy readability and extensibility.
     • Minor bugfixes etc.
  
  More detail can be found in the following paper:
  
  • W. Huang, K. Sankaranarayanan, R. J. Ribando, M. R. Stan, and K. Skadron. “An Improved Block-Based Thermal Model in HotSpot-4.0 with Granularity Considerations.” In Proceedings of the Workshop on Duplicating, Deconstructing, and Debunking, in conjunction with the 34th International Symposium on Computer Architecture (ISCA), June 2007 (pdf). Extended discussion and results can be found in this technical report.
  
  
• CHANGES IN VERSION 3.1
  1. Version 3.1 incorporates two major performance enhancements into the block model of HotSpot. The first is a math acceleration engine from Greg Link's HS3d tool that replaces HotSpot's vector and matrix function calls with vendor-provided BLAS and LAPACK math library calls. The second is the conversion of the fixed step-size transient Runge-Kutta solver into an adaptive step-size method.
  
  
• CHANGES IN RELEASE 3.0.2
  1. Release 3.0.2 fixes a bug in the grid model of HotSpot 3.0 that lead to erroneous discrepancies between the block and grid models.
  
  
• CHANGES IN RELEASE 3.0.1
  1. Release 3.0.1 fixes a few bugs in release 3.0, the most important of them being the way the dead space around the edge of the chip is modeled.
  2. This release provides a choice to the user for the mapping between the grid and block temperatures of the grid model.
  
  
• CHANGES SINCE VERSION 2.0
  1. A new grid-based thermal model that is better suited for transient thermal simulation of a large numbers of blocks, blocks of radically different sizes, and study of temperature gradients within blocks.
  2. 3-D modeling. The grid model allows modeling for individual layers within a die (device, metal, etc.) or stacked 3-D chips.
  3. HotFloorplan, an architecture-level floorplanning tool for pre-RTL design studies. It uses the classic simulated annealing algorithm and a thermal-aware objective function.
  4. Floorplan and thermal modeling of the dead space around the edge of the die due to scribe lines.
  5. Implementation of previously proposed, first-order wire-delay model for interconnects in the global and intermediate metal layers.
  6. A thermal visualization tool for the grid model that outputs the processor's thermal map as a color image in the SVG format.
  7. Improved and hence significantly different interfaces including:
     • Better command line support
     • Better specification of parameters through a configuration file
     • More modular code organization
     • Switch to C++ compiler as parts of the grid model are in C++
     • Improved documentation
  
  More detail can be found in this paper:
  
  • K. Sankaranarayanan, S. Velusamy, M.R. Stan, and K. Skadron.  "A Case for Thermal-Aware Floorplanning at the Microarchitectural Level."  To appear in The Journal of Instruction-Level Parallelism, June 2005. Available in pdf
    
• DIFFERENCES BETWEEN VERSIONS 1.0 and 2.0
  1. Modifications from the previous version
     • The demo "main" function in sim-template.c is now modified to read in power trace files and output temperature trace files.
     • The central heat spreader node, which was monolithic, is also divided now into multiple blocks - just like the die.
     • Bug fixes - 'getr' function and C_FACTOR modified.
  2. New in HotSpot 2.0
     • A thermal model for the interface material between the die and the heat spreader.
     • Validation of the HotSpot model against an actual test-chip.
     • New sample power trace input file - 'gcc.p' and temperature trace output file 'gcc.t'.
  
  More detail can be found in this paper:
  
  • W. Huang, M. R. Stan, K. Skadron, K. Sankaranarayanan, S. Ghosh, and S. Velusamy.  "Compact Thermal Modeling for Temperature-Aware Design."  In Proceedings of the 41st Design Automation Conference, June 2004. (pdf)

Last updated: 11 Apr. 2008

[ CS @ UVa | LAVA | HPLP ]